APA300(2008) View Datasheet(PDF) - Actel Corporation

Part Name

Description

Manufacturer

APA300
(Rev.:2008)

ProASICPLUS® Flash Family FPGAs

Actel Corporation 

ProASICPLUS Flash Family FPGAs

PLL Electrical Specifications

Parameter

Value

Notes

Frequency Ranges

Reference Frequency fIN (min.)

Reference Frequency fIN (max.)

OSC Frequency fVCO (min.)

OSC Frequency fVCO (max.)

Clock Conditioning Circuitry fOUT (min.)

Clock Conditioning Circuitry fOUT (max.)

Long Term Jitter Peak-to-Peak Max.*

1.5 MHz

180 MHz

24 MHz

180 MHz

6 MHz

180 MHz

Clock conditioning circuitry (min.) lowest input frequency

Clock conditioning circuitry (max.) highest input frequency

Lowest output frequency voltage controlled oscillator

Highest output frequency voltage controlled oscillator

Lowest output frequency clock conditioning circuitry

Highest output frequency clock conditioning circuitry

Temperature

Frequency MHz

25°C (or higher)

fVCO<10

±1%

10<fVCO<60

±2%

fVCO>60

±1%

Jitter(ps) = Jitter(%)*period

For example:

Jitter in picoseconds at 100 MHz

= 0.01 * (1/100E6) = 100 ps

0°C

±1.5%

±2.5%

±1%

–40°C

±2.5%

±3.5%

±1%

–55°C

±2.5%

±3.5%

±1%

Acquisition Time from Cold Start

Acquisition Time (max.)

Acquisition Time (max.)

Power Consumption

30 μs

80 μs

fVCO ≤ 40 MHz

fVCO > 40 MHz

Analog Supply Power (max.*)

Digital Supply Current (max.)

6.9 mW per PLL

7 μW/MHz

Duty Cycle

50% ±0.5%

Input Jitter Tolerance

5% input period (max. 5 ns)

Maximum jitter allowable on an input clock to

acquire and maintain lock.

Note: *High clock frequencies (>60 MHz) under typical setup conditions

v5.7

1-21

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