MR27V3266D View Datasheet(PDF) - Oki Electric Industry
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Description
Manufacturer
MR27V3266D Datasheet PDF : 36 Pages
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1 Semiconductor
REVISION HISTORY
Revision 2.0
Revision 2.1
MR27V3266D
1. Page 13
Active Standby Current (ICC1) was revised from 50mA to 100mA.
2. Page 14
Regarding Note 1, it was revised from " .... internal command controller to cease the preceding command operation
to keep output buffer high-Z state instead of the null output " to " .... internal command controller to cease the
preceding command operation " ( underlined portion was eliminated. ).
3. Page 24
Regarding the timing diagram of " Burst Read / Interrupt II , DQ timing diagram was revised as bellow :
High-Z
DQ
Qa0 Qa1 Qa2 Qa3
Qb0 Qb1 Qb2 Qb3
High-Z
DQ
Invalid State
Qa0 Qa1 Qa2 Qa3
Qb0 Qb1 Qb2 Qb3
Revision 2.1
Revision 2.2
1. Page 14
tRCD (" Row Active " to " Read " Delay Time ) was revised from 1CLK to 2CLK.
2. Page 17
Contents of this page ( timing diagram of " Random Access with Gapless Burst ") was eliminated.
Revision 2.2
Revision 2.3
1. Page 5 , 8
All descriptions of the case in " AMPX is high " were eliminated.
2. Page 27
All function table of " Address Multiplexed " and relational notes (2,3 and 4) were eliminated.
3. Page 29 , 30
All timing parameters regarding " Address Multiplexed " and relational notes (1 and 2) were eliminated.
4. Page 31 , 32 , 33 , 34
All timing waveforms regarding " Address Multiplexed " were eliminated.
Revision 2.3
Revision 2.4
1. Page 14
tAC (Data to Valid Output Delay ) was revised from 10ns to 9ns.
tOH (Data Output Hold Time ) was revised from 4ns to 3ns.
tSI (Input Setup Time ) was revised from 4ns to 3ns.
tHI (Input Hold Time ) was revised from 2ns to 1.5ns.
tRCD (" Row Active " to " Read " Delay Time ) =1 CLK was added in case of up to 50MHz.
2. Page 17
Contents of this page ( timing diagram of " Random Access with Gapless Burst ") was republished in case of
up to 50MHz.
August , 1999
Revision 2.4
32M Synchronous OTP
36
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