AS3930 View Datasheet(PDF) - austriamicrosystems AG
Part Name
Description
Manufacturer
AS3930 Datasheet PDF : 32 Pages
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AS3930
Datasheet - Detailed Description
8.1.4 Data Receiving
After a successful wake-up the chip enters the data receiving mode. In this mode, the chip can be retained as a normal OOK receiver. The
received data are displayed on the DAT pin. It is possible to put the chip back in to listening mode either with a direct command (CLEAR_WAKE,
see Table 12) or by using the timeout feature. This feature automatically sets the chip back to listening mode after a certain time defined in the
R7<7:5>.
8.2 System and Block Specification
8.2.1 Main Logic and SDI
Table 6. Register Table
7
6
5
4
3
R0
n.a.
ON_OFF
Reserved
R1
ABS_HY AGC_TLIM AGC_UD ATT_ON
n.a.
R2
S_ABSH
W_PAT_T<1:0>
Reserved
R3
HY_20m HY_POS
FS_SLC<2:0>
R4
T_OFF<1:0>
R_VAL<1:0>
R5
TS2<7:0>
R6
TS1<7:0>
R7
T_OUT<2:0>
R8
n.a.
R9
n.a.
R10
n.a.
Reserved
R11
n.a.
R12
n.a.
R13
F_WAKE
2
1
0
EN_A
PWD
EN_PAT2 EN_WPAT
EN_RTC
S_WU1<1:0>
FS_ENV<2:0>
GR<3:0>
T_HBIT<4:0>
T_AUTO<2:0>
RSSI1<4:0>
Register Table Description and Default Values.
Table 7. Description and Default Values
Register
R0<5>
R0<4>
R0<3>
R0<2>
Name
ON_OFF
MUX_123
Reserved
Reserved
Type Default Value
Description
R/W
0
On/Off operation mode. (Duty-cycle defined in the register R4<7:6>)
R/W
0
Reserved (it is not allowed to set this bit to 1)
1
Reserved
1
Reserved
R0<1>
EN_A
R/W
R0<0>
PWD
R/W
R1<7>
ABS_HY
R/W
R1<6>
AGC_TLIM
R/W
R1<5>
AGC_UD
R/W
R1<4>
ATT_ON
R/W
R1<3>
Reserved
R1<2>
EN_PAT2
R/W
R1<1>
EN_WPAT
R/W
R1<0>
EN_RTC
R/W
1
Channel enable
0
Power down
0
Data slicer absolute reference
0
AGC acting only on the first carrier burst
1
AGC operating in both directions (up-down)
0
Antenna damper enable
0
Reserved
0
Double wake-up pattern correlation
1
Data correlation enable
1
Crystal oscillator enable
www.ams.com/LF-Receiver/AS3930
Revision 1.5
12 - 32
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