AS3931 View Datasheet(PDF) - austriamicrosystems AG
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AS3931 Datasheet PDF : 31 Pages
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AS3931
Datasheet - Electrical Characteristics
Table 3. Electrical Characteristics
Symbol
Parameter
Conditions
Min Typ Max Units
TDVCH
Data valid to pos. Clock
edge
VREG = 2.4 V to 3.5 V11
100
ns
TCHDI
pos. Clock edge to Data
invalid
VREG = 2.4 V to 3.5 V11
100
ns
TSHCH
Select active to pos. Clock
edge
VREG = 2.4 V to 3.5 V11
100
ns
lid TCHSL
pos. Clock to Select
inactive
VREG = 2.4 V to 3.5 V11
100
ns
TSL
Select low time
VREG = 2.4 V to 3.5 V11
500
ns
a 1. The half-bit rate correlates with the crystal oscillator clock frequency fclk as follows: BR = fCLK/12
v 2. The Manchester bit rate correlates with the Half-Bit Rate as follows: BM = BR/2
3. Code word can be changed by metal option
ill 4. 8 preamble half-bits are equivalent to 4 manchester bits
5. VREG output may not be used as a supply for other circuits
6. This is the internal Power on Reset time generated by the chip. To ensure proper start-up conditions, the supply voltage VCC must be
t ramped up to its final value during TPOR
G 7. This is the additional operating current when the RSSI buffer is activated without load
s 8. ΔVCC means a hard step of the supply voltage down to a lower value by an amount of ΔVCC; after such a step, the analog circuits in the
A t chip take some time to recover for working properly again. The maximum step value is listed.
9. Crystal tolerance: 100ppm
s n 10.Values refer to production test
11.If regulator is on, then VREG = 2.4 V; If regulator is off, then VREG = VCC, where VCC = 2.4 V to 3.5 V
e 12.The RSSI step is the change of the RSSI output voltage when the input signal amplitude changes from 0 to specified value
m t 13.Time to step from initial RSSI value to 95% of the final value
Technicaal con 14.ChA may be any channel 1 – 3, whereas ChB may be any other remaining channel.
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