ASC7621 View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
ASC7621 Datasheet PDF : 50 Pages
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aSC7621
R/W
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
De-
fault
Value
(hex)
Zone 2 Range/
60h R/W Fan 2
Frequency
RAN3 RAN2 RAN1 RAN0 HLFRQ FRQ2
FRQ1
FRQ0
C3 X
Zone 3 Range/
61h R/W Fan 3
Frequency
RAN3 RAN2 RAN1 RAN0 HLFRQ FRQ2
FRQ1
FRQ0
C3 X
Min/Off, Zone 1
62h R/W Spike
Smoothing
OFF3
OFF2
OFF1
RES
ZN1E
ZN1-2
ZN1-1
ZN1-0
00 X
Zone 2 / Zone 3
63h R/W Spike
Smoothing
ZN2E
ZN2-2 ZN2-1 ZN2-0
ZN3E
ZN3-2
ZN3-1
ZN3-0
00 X
64h
R/W
Fan 1 PWM
Minimum
7
6
5
4
3
2
1
0
80
X
65h
R/W
Fan 2 PWM
Minimum
7
6
5
4
3
2
1
0
80
X
66h
R/W
Fan 3 PWM
Minimum
7
6
5
4
3
2
1
0
80
X
67h
R/W
Zone 1 Fan
Temp Limit
7
6
5
4
3
2
1
0
5A X
68h
R/W
Zone 2 Fan
Temp Limit
7
6
5
4
3
2
1
0
5A X
69h
R/W
Zone 3 Fan
Temp Limit
7
6
5
4
3
2
1
0
5A X
6Ah
R/W
Zone 1 Temp
Absolute Limit
7
6
5
4
3
2
1
0
64
X
6Bh
R/W
Zone 2 Temp
Absolute Limit
7
6
5
4
3
2
1
0
64
X
6Ch
R/W
Zone 3 Temp
Absolute Limit
7
6
5
4
3
2
1
0
64
X
6Dh
R/W
Zone 1, Zone 2
Hysteresis
H1-3
H1-2
H1-1
H1-0
H2-3
H2-2
H2-1
H2-0
44
X
6Eh
R/W
Zone 3, Zone 4
Hysteresis
H3-3
H3-2
H3-1
H3-0
H4-3
H4-2
H4-1
H4-0
44 X
6Fh
R/W
XOR Tree
Enable
RES
RES
RES
RES
RES
RES
RES
XEN
00 X
75h
R/W
Fan Spin-up
Mode
Tach4 Tach3/4 Tach2 Tach1
Disable Disable Disable Disable
RES
PWM3SU PWM2SU PWM1SU
00
X
Notes:
1. Reserved bits will always return 0 when read, X-bits in readings may be ignored.
2. When register 40h is locked, all bits are locked except 0 and 3 which remain user changeable.
3. Two-byte or extended resolution temperature, voltage and tachometer values are protected from changing when only one of
the bytes is read. The implementation of a data word latch involves the register pairs in the table below. When one of the
address pairs is read, the mating data is latched at the same time. The next SMBus access MUST be the mating address
or the latch will be released. This implementation allows that the data may be read in the order of LS-MS or MS-LS and the
pair will remain coherent.
© Andigilog, Inc. 2006
- 15 -
www.andigilog.com
October 2006 - 70A06010
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