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AT24C512B-10PU-1.8 View Datasheet(PDF) - Atmel Corporation

Part Name
Description
Manufacturer
AT24C512B-10PU-1.8
Atmel
Atmel Corporation Atmel
AT24C512B-10PU-1.8 Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
STANDBY MODE: The AT24C512B features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-
wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
Figure 2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
SCL
SDA
8th BIT
WORDn
ACK
STOP
CONDITION
twr(1)
START
CONDITION
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
6 AT24C512B [Preliminary]
5112A–SEEPR–8/05

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