Figure 7-5. Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
tF
tLOW
tHIGH
tLOW
SDA IN
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tAA
tDH
SDA OUT
tR
tSU.STO
tBUF
Figure 7-6. Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th Bit
ACK
WORDN
Stop
Condition
(1)
tWR
Start
Condition
Note: 1. The write cycle time tWR is the time from a valid Stop condition of a write sequence to the end of the internal
clear/write cycle.
AT24CS01/02 [DATASHEET]
9
Atmel-8815D-SEEPROM-AT24CS01-02-Datasheet_082014