AT25DF321A View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT25DF321A

32-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory

Atmel Corporation 

Figure 2-1. 8-SOIC (Top View)

CS 1

SO (SOI) 2

WP 3

GND 4

8 VCC

7 HOLD

6 SCK

5 SI (SIO)

3. Block Diagram

Figure 3-1. Block Diagram

Figure 2-2. 8-UDFN (Top View)

CS 1

SO (SOI) 2

WP 3

GND 4

8 VCC

7 HOLD

6 SCK

5 SI (SIO)

CS

SCK

SI (SIO)

SO (SOI)

WP

HOLD

INTERFACE

CONTROL

AND

LOGIC

CONTROL AND

PROTECTION LOGIC

Y-DECODER

X-DECODER

I/O BUFFERS

AND LATCHES

SRAM

DATA BUFFER

Y-GATING

FLASH

MEMORY

ARRAY

4. Memory Array

To provide the greatest flexibility, the memory array of the Atmel® AT25DF321A can be erased in four levels of granularity

including a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each sector

can be individually protected from program and erase operations. The size of the physical sectors is optimized for both code

and data storage applications, allowing both code and data segments to reside in their own isolated regions. The Memory

Architecture Diagram illustrates the breakdown of each erase level as well as the breakdown of each physical sector.

4

Atmel AT25DF321A

3686D–DFLASH–12/09

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