AT89S51-24 View Datasheet(PDF) - Atmel Corporation
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AT89S51-24 Datasheet PDF : 32 Pages
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Table 5-2. AUXR: Auxiliary Register
AUXR
Address = 8EH
Not Bit Addressable
–
–
– WDIDLE DISRTO
–
Bit
7
6
5
4
3
2
Reset Value = XXX00XX0B
–
DISALE
1
0
–
DISALE
DISRTO
WDIDLE
WDIDLE
0
1
Reserved for future expansion
Disable/Enable ALE
DISALE
Operating Mode
0
ALE is emitted at a constant rate of 1/6 the oscillator frequency
1
ALE is active only during a MOVX or MOVC instruction
Disable/Enable Reset-out
DISRTO
0
Reset pin is driven High after WDT times out
1
Reset pin is input only
Disable/Enable WDT in IDLE mode
WDT continues to count in IDLE mode
WDT halts counting in IDLE mode
Dual Data Pointer Registers: To facilitate accessing both internal and external data memory,
two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-
83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.
The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the
respective Data Pointer Register.
Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF
is set to “1” during power up. It can be set and rest under software control and is not affected by
reset.
8
AT89S51
2487C–MICRO–03/05
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