AT89S51-24 View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT89S51-24

8-bit Microcontroller with 4K Bytes In-System Programmable Flash

Atmel Corporation 

AT89S51

Table 5-3. AUXR1: Auxiliary Register 1

AUXR1

Address = A2H

Not Bit Addressable

–

–

–

–

–

Bit

7

6

5

4

3

Reset Value = XXXXXXX0B

–

–

2

1

DPS

0

–

DPS

Reserved for future expansion

Data Pointer Register Select

DPS

0

Selects DPTR Registers DP0L, DP0H

1

Selects DPTR Registers DP1L, DP1H

6. Memory Organization

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K

bytes each of external Program and Data Memory can be addressed.

6.1 Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory.

On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H through FFFH

are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to

external memory.

6.2 Data Memory

The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct

and indirect addressing modes. Stack operations are examples of indirect addressing, so the

128 bytes of data RAM are available as stack space.

7. Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be subjected to

software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset

(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user

must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When

the WDT is enabled, it will increment every machine cycle while the oscillator is running. The

WDT timeout period is dependent on the external clock frequency. There is no way to disable

the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-

flows, it will drive an output RESET HIGH pulse at the RST pin.

7.1 Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register

(SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH

and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches

16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every

machine cycle while the oscillator is running. This means the user must reset the WDT at least

9

2487C–MICRO–03/05

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