AT89S8252 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT89S8252 Datasheet PDF : 32 Pages
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Serial Downloading (Continued)
24 MHz oscillator clock, the maximum SCK frequency is
600 kHz.
Serial Programming Algorithm
To program and verify the AT89S8252 in the serial pro-
gramming mode, the following sequence is recom-
mended:
1. Power-up sequence:
Apply power between VCC and GND pins with all other
pins floating.
Set RST pin to ’H’.
If a crystal is not connected across pins XTAL1 and
XTAL2, apply a 4 MHz to 24 MHz clock to XTAL1 pin
and wait for at least 10 milliseconds.
2. Enable serial programming by sending the Program-
ming Enable serial instruction to pin MOSI/P1.5. The
frequency of the shift clock supplied at pin SCK/P1.7
needs to be less than the CPU clock at XTAL1 di-
vided by 40.
Instruction Set
3. The Code or Data array is programmed one byte at a
time by supplying the address and data together with
the appropriate Write instruction. The selected mem-
ory location is first automatically erased before new
data is written.
4. Any memory location can be verified by using the
Read instruction which returns the content at the se-
lected address at serial output MISO/P1.6.
5. At the end of a programming session, RST can be set
low to commence normal operation.
6. Power-off sequence (if needed):
Set XTAL1 to ’L’ (if a crystal is not used).
Set RST to ’L’.
Float all other I/O pins.
Turn VCC power off.
Serial Programming Instruction
The Instruction Set for Serial Programming follows a 3
byte protocol and is shown in the following table:
Instruction
Input Format
Operation
MSB
LSB
Programming Enable
1010
0101
xxxx
1100
0011
xxxx
Enable serial programming interface after RST
goes high.
Chip Erase
1010 1100
xxxx x100 Chip erase both 8K & 2K memory arrays.
xxxx xxxx
Read Code Memory
aaaa
low
xxxx
a001
addr
xxxx
Read data from Code memory array at the
selected address. The 5 MSBs of the first byte
are the high order address bits. The low order
address bits are in the second byte. Data are
available at pin MISO during the third byte.
Write Code Memory
aaaa a010 Write data to Code memory location at selected
low addr address. The address bits are the 5 MSBs of the
data in first byte together with the second byte.
Read Data Memory
00aa a101 Read data from Data memory array at selected
low addr address. Data are available at pin MISO during
xxxx xxxx the third byte.
Write Data Memory
00aa
low
data
a110
addr
in
Write data to Data memory location at selected
address.
Write Lock Bits
1010
LLLx
BBB
123
xxxx
1100
x111 Write lock bits.
Set LB1, LB2 or LB3 = ’0’ to program lock bits.
xxxx
Notes: 1. DATA polling is used to indicate the end of a write cy-
cle, which typically takes less than 2.5 ms.
2. ‘aaaaa’ = high order address.
3. ’x’ = don’t care.
20
AT89S8252
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