AT90LS2333-4AC View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT90LS2333-4AC

8-bit Microcontroller with 2K/4K bytes In-System Programmable Flash

Atmel Corporation 

Instruction Set Summary (Continued)

Mnemonics

Operands Description

DATA TRANSFER INSTRUCTIONS

MOV

LDI

LD

LD

LD

LD

Rd, Rr

Rd, K

Rd, X

Rd, X+

Rd, - X

Rd, Y

Move Between Registers

Load Immediate

Load Indirect

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

LD

LD

LDD

Rd, Y+

Rd, - Y

Rd,Y+q

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

LD

Rd, Z

Load Indirect

LD

Rd, Z+

Load Indirect and Post-Inc.

LD

Rd, -Z

Load Indirect and Pre-Dec.

LDD

LDS

ST

ST

Rd, Z+q

Rd, k

X, Rr

X+, Rr

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Store Indirect and Post-Inc.

ST

- X, Rr

Store Indirect and Pre-Dec.

ST

Y, Rr

Store Indirect

ST

Y+, Rr

Store Indirect and Post-Inc.

ST

STD

ST

ST

- Y, Rr

Y+q,Rr

Z, Rr

Z+, Rr

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

Store Indirect and Post-Inc.

ST

STD

STS

LPM

IN

OUT

PUSH

-Z, Rr

Z+q,Rr

k, Rr

Rd, P

P, Rr

Rr

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

In Port

Out Port

Push Register on Stack

POP

Rd

Pop Register from Stack

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Set Bit in I/O Register

CBI

P,b

Clear Bit in I/O Register

LSL

Rd

Logical Shift Left

LSR

Rd

Logical Shift Right

ROL

Rd

ROR

Rd

ASR

Rd

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

SWAP

Rd

BSET

s

BCLR

s

Swap Nibbles

Flag Set

Flag Clear

BST

BLD

SEC

CLC

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

Clear Carry

SEN

CLN

SEZ

Set Negative Flag

Clear Negative Flag

Set Zero Flag

CLZ

SEI

CLI

SES

Clear Zero Flag

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

CLS

SEV

Clear Signed Test Flag

Set Twos Complement Overflow.

CLV

SET

CLT

SEH

Clear Twos Complement Overflow

Set T in SREG

Clear T in SREG

Set Half Carry Flag in SREG

CLH

NOP

SLEEP

Clear Half Carry Flag in SREG

No Operation

Sleep

WDR

Watchdog Reset

Operation

Rd ← Rr

Rd ← K

Rd ← (X)

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

(X) ← Rr

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

(Z) ← Rr

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

(k) ← Rr

R0 ← (Z)

Rd ← P

P ← Rr

STACK ← Rr

Rd ← STACK

I/O(P,b) ← 1

I/O(P,b) ← 0

Rd(n+1) ← Rd(n), Rd(0) ← 0

Rd(n) ← Rd(n+1), Rd(7) ← 0

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Rd(n) ← Rd(n+1), n=0..6

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C←1

C←0

N←1

N←0

Z←1

Z←0

I←1

I←0

S←1

S←0

V←1

V←0

T←1

T←0

H←1

H←0

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

Flags

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

Z,C,N,V

Z,C,N,V

Z,C,N,V

Z,C,N,V

Z,C,N,V

None

SREG(s)

SREG(s)

T

None

C

C

N

N

Z

Z

I

I

S

S

V

V

T

T

H

H

None

None

None

#Clocks

1

1

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

3

1

1

2

2

2

2

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

3

1

10 AT90S/LS2333 and AT90S/LS4433

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