AT90S4434-8PC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT90S4434-8PC
Atmel Corporation
AT90S4434-8PC Datasheet PDF : 10 Pages
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Mnemonics Operands Description
DATA TRANSFER INSTRUCTIONS
MOV
LDI
LD
Rd, Rr
Rd, K
Rd, X
Move Between Registers
Load Immediate
Load Indirect
LD
Rd, X+
Load Indirect and Post-Inc.
LD
Rd, - X
Load Indirect and Pre-Dec.
LD
Rd, Y
Load Indirect
LD
LD
LDD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
LD
LD
LDD
Rd, Z+
Rd, -Z
Rd, Z+q
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
LDS
Rd, k
Load Direct from SRAM
ST
X, Rr
Store Indirect
ST
X+, Rr
Store Indirect and Post-Inc.
ST
- X, Rr
Store Indirect and Pre-Dec.
ST
Y, Rr
Store Indirect
ST
Y+, Rr
Store Indirect and Post-Inc.
ST
- Y, Rr
Store Indirect and Pre-Dec.
STD
ST
ST
Y+q,Rr
Z, Rr
Z+, Rr
Store Indirect with Displacement
Store Indirect
Store Indirect and Post-Inc.
ST
STD
STS
LPM
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
IN
OUT
PUSH
Rd, P
P, Rr
Rr
In Port
Out Port
Push Register on Stack
POP
Rd
Pop Register from Stack
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
CBI
P,b
Clear Bit in I/O Register
LSL
Rd
Logical Shift Left
LSR
Rd
Logical Shift Right
ROL
Rd
ROR
Rd
ASR
Rd
SWAP
Rd
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
BSET
BCLR
BST
s
s
Rr, b
Flag Set
Flag Clear
Bit Store from Register to T
BLD
SEC
CLC
Rd, b
Bit load from T to Register
Set Carry
Clear Carry
SEN
CLN
SEZ
CLZ
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
SEI
CLI
SES
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
CLS
SEV
CLV
SET
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
CLT
SEH
CLH
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
NOP
SLEEP
WDR
No Operation
Sleep
Watchdog Reset
Operation
Rd โ Rr
Rd โ K
Rd โ (X)
Rd โ (X), X โ X + 1
X โ X - 1, Rd โ (X)
Rd โ (Y)
Rd โ (Y), Y โ Y + 1
Y โ Y - 1, Rd โ (Y)
Rd โ (Y + q)
Rd โ (Z)
Rd โ (Z), Z โ Z+1
Z โ Z - 1, Rd โ (Z)
Rd โ (Z + q)
Rd โ (k)
(X) โ Rr
(X) โ Rr, X โ X + 1
X โ X - 1, (X) โ Rr
(Y) โ Rr
(Y) โ Rr, Y โ Y + 1
Y โ Y - 1, (Y) โ Rr
(Y + q) โ Rr
(Z) โ Rr
(Z) โ Rr, Z โ Z + 1
Z โ Z - 1, (Z) โ Rr
(Z + q) โ Rr
(k) โ Rr
R0 โ (Z)
Rd โ P
P โ Rr
STACK โ Rr
Rd โ STACK
I/O(P,b) โ 1
I/O(P,b) โ 0
Rd(n+1) โ Rd(n), Rd(0) โ 0
Rd(n) โ Rd(n+1), Rd(7) โ 0
Rd(0)โC,Rd(n+1)โ Rd(n),CโRd(7)
Rd(7)โC,Rd(n)โ Rd(n+1),CโRd(0)
Rd(n) โ Rd(n+1), n=0..6
Rd(3..0)โRd(7..4),Rd(7..4)โRd(3..0)
SREG(s) โ 1
SREG(s) โ 0
T โ Rr(b)
Rd(b) โ T
Cโ1
Cโ0
Nโ1
Nโ0
Zโ1
Zโ0
Iโ1
Iโ0
Sโ1
Sโ0
Vโ1
Vโ0
Tโ1
Tโ0
Hโ1
Hโ0
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
8 AT90S/LS4434 and AT90S/LS8535
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
#Clocks
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
1
1
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
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