ATC18M View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATC18M

0.18 µm CMOS Cell-based ASIC for Military Use

Atmel Corporation 

Delays to tri-state are defined as delay to turn off (VGS < VT) of the driving devices.

Output pad drain current corresponds to the output current of the pad when the output

voltage is VOL or VOH. The output resistor of the pad and the voltage drop due to access

resistors (in and out of the die) are taken into account. In order to have accurate timing

estimates, all characterization has been run on electrical netlists extracted from the lay-

out database.

Standard Cell Library

SClib

The Atmel Standard Cell Library, SClib, contains a comprehensive set of a combination

of logic and storage cells. The SClib library includes cells that belong to the following

categories:

• Buffers and Gates

• Multiplexers

• Flip-flops

• Scan Flip-flops

• Latches

• Adders and Subtractors

Decoding the Cell Name

Table 2 shows the naming conventions for the cells in the SClib library. Each cell name

begins with either a two-, three-, or four-letter code that defines the type of cell. This

indicates the range of standard cells available.

Table 2. Cell Codes

Code

Description

AD

Adder

AH

Half Adder

AS

Adder/Subtractor

AN

AND Gate

AOI

AND-OR-Invert Gate

AON

AND-OR-AND-Invert Gates

AOR

AND-OR Gate

BUFB

Balanced Buffer

BUFF

Non-Inverting Buffer

BUFT

Non-Inverting Tri-state Buffer

CG

Carry Generator

CLK2

Clock Buffer

DF

D Flip-flop

DLA

Dual Input Latches

H...

SEU Hardened Versions

INV0

Inverter

Code

INVB

INVT

LA

MI

MX

ND

NR

OAI

OAN

OR

ORA

SD

SRLA

SU

XN

XR

Description

Balanced Inverter

Inverting Tri-state Buffer

D Latch

Inverting Multiplexer

Multiplexer

NAND Gate

NOR Gate

OR-AND-Invert Gate

OR-AND-OR-Invert Gates

OR Gate

OR-AND Gate

Multiplexed Scan D Flip-flop

Set/Reset Latches with NAND input

Subtractor

Exclusive NOR Gate

Exclusive OR Gate

2 ATC18M

4262A–AERO–07/03

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