ATC18M View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATC18M Datasheet PDF : 8 Pages
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Design Flow
ATC18M
Though only MODELSIM and NCSIM will be used as the golden simulators, the design
kit will include the data and libraries needed for the following tools:
Tool
GATEAID2®
MODELSIM®
NCSIM®
DESIGN COMPILER®
BUILDGATES®
POWER COMPILER
DFT SUITE
FE-ULTRA
PRIMETIME®
FORMALITY
Supplier
Atmel
Mentor
Cadence
Synopsys®
Cadence®
Synopsys
Mentor®
Cadence
Synopsys
Synopsys
Purpose
Atmel Support tools
VHDL®/VITAL® RTL + gate level
simulation
VERILOG® RTL + gate level simulation
HDL synthesis
HDL synthesis
Synthesis power optimization
Scan+ATPG (FastScan), JTAG (BSD-
Architect), BIST (MBIST-Architect)
Floor-planning, physical knowledgeable
synthesis, layout prototyping
Static timing analysis
Equivalence checking, formal proof
The Design flow can be described in two sections:
• The front-end done at the customer’s premises
• The back-end at Atmel Technical Centers, provided that the front-end activity has
been validated and accepted by Atmel during the Logic Review (LR) meeting.
The following table lists the activities and tools that will be used during the front-end
design.
Function
RTL SIMULATION
CODE COVERAGE
RTL TO GATE SYNTHESIS
POWER OPTIMIZATION
POWER ANALYSIS
TEST INSERTION + ATPG
GATE LEVEL SIMULATION
NETLIST TRANSLATION
DESIGN RULES CHECK
Tool
MODELSIM
NC-SIM
VHDL-COVER
DESIGN-COMPILER
BUILD-GATES
POWER-COMPILER
PRIME-POWER
DFT-SUITE
MODELSIM
NC-SIM
NETCVT
STAR
Supplier
Mentor
Cadence
Transeda
Synopsys
Cadence
Synopsys
Synopsys
Mentor
Mentor
Cadence
Atmel
Atmel
5
4262A–AERO–07/03
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