ATF1508ASVL-20 View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATF1508ASVL-20

High performance EE PLD

Atmel Corporation 

Design Software

Support

All ATF1508 also have an optional power-down mode. In this mode, current drops to

below 10 mA. When the power-down option is selected, either PD1 or PD2 pins (or

both) can be used to power down the part. The power-down option is selected in the

design source file. When enabled, the device goes into power-down when either PD1 or

PD2 is high. In the power-down mode, all internal logic signals are latched and held, as

are any enabled outputs.

All pin transitions are ignored until the PD pin is brought low. When the power-down fea-

ture is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However,

the pin’s macrocell may still be used to generate buried foldback and cascade logic

signals.

All power-down AC characteristic parameters are computed from external input or I/O

pins, with reduced-power bit turned on. For macrocells in reduced-power mode

(reduced-power bit turned on), the reduced-power adder, tRPA, must be added to the AC

parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP.

Each output also has individual slew rate control. This may be used to reduce system

noise by slowing down outputs that do not need to operate at maximum speed. Outputs

default to slow switching, and may be specified as fast switching in the design file.

ATF1508ASV(L) designs are supported by several third-party tools. Automated fitters

allow logic synthesis using a variety of high-level description languages and formats.

Power-up Reset

The ATF1508ASV is designed with a power-up reset, a feature critical for state machine

initialization. At a point delayed slightly from VCC crossing VRST, all registers will be ini-

tialized, and the state of each output will depend on the polarity of its buffer. However,

due to the asynchronous nature of reset and uncertainty of how VCC actually rises in the

system, the following conditions are required:

1. The VCC rise must be monotonic,

2. After reset occurs, all input and feedback setup times must be met before driving

the clock pin high, and,

3. The clock must remain stable during TD.

The ATF1508ASV has two options for the hysteresis about the reset level, VRST, Small

and Large. To ensure a robust operating environment in applications where the device

is operated near 3.0V, Atmel recommends that during the fitting process users configure

the device with the Power-up Reset hysteresis set to Large. For conversions, Atmel

POF2JED users should include the flag “-power_reset” on the command line after “file-

name.POF”. To allow the registers to be properly reinitialized with the Large hysteresis

option selected, the following condition is added:

4. If VCC falls below 2.0V, it must shut off completely before the device is turned on

again.

When the Large hysteresis option is active, ICC is reduced by several hundred micro-

amps as well.

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF1508ASV(L) fuse

patterns. Once programmed, fuse verify is inhibited. However, User Signature and

device ID remains accessible.

8 ATF1508ASV(L)

1408H–PLD–7/05

Share Link: