ATF1516AS(1999) View Datasheet(PDF) - Atmel Corporation
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ATF1516AS Datasheet PDF : 13 Pages
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Product Terms and Select MUX
Each ATF1516AS macrocell has five product terms. Each
product term receives as its inputs all signals from both the
global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the
five product terms as needed to the macrocell logic gates
and control signals. The PTMUX programming is deter-
mined by the design compiler, which selects the optimum
macrocell configuration.
OR/XOR/CASCADE Logic
The ATF1516AS’s logic structure is designed to efficiently
support all types of logic. Within a single macrocell, all the
product terms can be routed to the OR gate, creating a 5-
input AND/OR sum term. With the addition of the CASIN
from neighboring macrocells, this can be expanded to as
many as 40 product terms with little additional delay.
The macrocell’s XOR gate allows efficient implementation
of compare and arithmetic functions. One input to the XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high or low level. For combinato-
rial outputs, the fixed level input allows polarity selection.
For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used
to emulate T- and JK-type flip-flops.
Flip-flop
The ATF1516AS’s flip-flop has very flexible data and con-
trol functions. The data input can come from either the
XOR gate, from a separate product term or directly from
the I/O pin. Selecting the separate product term allows cre-
ation of a buried registered feedback within a combinatorial
output macrocell. (This feature is automatically imple-
mented by the fitter software). In addition to D, T, JK and
SR operation, the flip-flop can also be configured as a flow-
through latch. In this mode, data passes through when the
clock is high and is latched when the clock is low.
The clock itself can be either the Global CLK signal (GCK)
or an individual product term. The flip-flop changes state on
the clock’s rising edge. When the GCK signal is used as
the clock, one of the macrocell product terms can be
selected as a clock enable. When the clock enable function
is active and the enable signal (product term) is low, all
clock edges are ignored. The flip-flop’s asynchronous reset
signal (AR) can be either the Global Clear (GCLEAR), a
product term, or always off. AR can also be a logic OR of
GCLEAR with a product term. The asynchronous preset
(AP) can be a product term or always off.
Output Select and Enable
The ATF1516AS macrocell output can be selected as reg-
istered or combinatorial. The buried feedback signal can be
either combinatorial or registered signal regardless of
whether the output is combinatorial or registered.
The output enable multiplexer (MOE) controls the output
enable signals. Any buffer can be permanently enabled for
simple output operation. Buffers can also be permanently
disabled to allow use of the pin as an input. In this configu-
ration all the macrocell resources are still available,
including the buried feedback, expander and CASCADE
logic. The output enable for each macrocell can be
selected as either of the two dedicated OE input pins as an
I/O pin configured as an input, or as an individual product
term.
Global Bus/Switch Matrix
The global bus contains all input and I/O pin signals as well
as the buried feedback signal from all 256 macrocells.
The switch matrix in each logic block receives as its inputs
all signals from the global bus. Under software control, up
to 40 of these signals can be selected as inputs to the logic
block.
Foldback Bus
Each macrocell also generates a foldback product term.
This signal goes to the regional bus and is available to 16
macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The 16 foldback terms in each
region allow generation of high fan-in sum terms (up to 21
product terms) with little additional delay.
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ATF1516AS(L)
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