ATF16V8CZ(1998) View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATF16V8CZ Datasheet PDF : 10 Pages
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Input Test Waveforms and
Measurement Levels:
ATF16V8CZ
Output Test Loads
tR, tF < 1.5 ns (10% to 90%)
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Note: Similar devices are tested with slightly different loads.
These load differences may affect output signals’ delay and
slew rate. Atmel devices are tested with sufficient margins
to meet compatible devices.
Typ
Max
Units
Conditions
CIN
5
8
pF
VIN = 0V
COUT
6
8
pF
VOUT = 0V
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power Up Reset
The ATF16V8CZ’s registers are designed to reset during
power up. At a point delayed slightly from VCC crossing
VRST, all registers will be reset to the low state. As a result,
the registered output state will always be high on power-
up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the un-
certainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1) The VCC rise must be monotonic, from below .7 volts,
2) After reset occurs, all input and feedback setup times
must be met before driving the clock term high, and
Parameter Description Typ
3) The signals from which the clock is derived must re-
main stable during tPR.
tPR
Power-Up
Reset Time
600
Power-Up
VRST Reset
3.8
Voltage
Max Units
1,000 ns
4.5
V
5
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