ATF16V8B View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATF16V8B

High-performance EE PLD

Atmel Corporation 

ATF16V8B/BQ/BQL

4.6 Power-up Reset

The registers in the ATF16V8Bs are designed to reset during power-up. At a point delayed

slightly from VCC crossing VRST, all registers will be reset to the low state. As a result, the regis-

tered output state will always be high on power-up.

This feature is critical for state machine initialization. However, due to the asynchronous nature

of reset and the uncertainty of how VCC actually rises in the system, the following conditions are

required:

1. The VCC rise must be monotonic,

2. After reset occurs, all input and feedback setup times must be met before driving the

clock pin high, and

3. The clock must remain stable during tPR.

Figure 4-1. Power-up Reset Waveforms

Table 4-2.

Parameter

tPR

VRST

Power-up Reset Parameters

Description

Power-up

Reset Time

Power-up

Reset Voltage

Typ

Max

600

1,000

3.8

4.5

Units

ns

V

4.7 Preload of Registered Outputs

The ATF16V8B’s registers are provided with circuitry to allow loading of each register with either

a high or a low. This feature will simplify testing since any state can be forced into the registers

to control test sequencing. A JEDEC file with preload is generated when a source file with vec-

tors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically

by most of the approved programmers after the programming.

5. Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF16V8B fuse patterns. Once

programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains

accessible.

The security fuse should be programmed last, as its effect is immediate.

7

0364J–PLD–7/05

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