ATMEGA163 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATMEGA163 Datasheet PDF : 187 Pages
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Figure 5. The ATmega163 AVR RISC Architecture
8K X 16
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Data Bus 8-bit
Status
and Control
32 x 8
General
Purpose
Registrers
ALU
1024 x 8
Data
SRAM
512 x 8
EEPROM
32
I/O Lines
Interrupt
Unit
SPI
Unit
Serial
UART
Two-wire Serial
Interface
8-bit
Timer/Counter
16-bit
Timer/Counter
with PWM
8-bit
Timer/Counter
with PWM
Watchdog
Timer
A/D Converter
Analog
Comparator
The AVR uses a Harvard architecture concept – with separate memories and buses for
program and data. The Program memory is executed with a two stage pipeline. While
one instruction is being executed, the next instruction is pre-fetched from the Program
memory. This concept enables instructions to be executed in every clock cycle. The
Program memory is In-System Re-programmable Flash memory.
With the jump and call instructions, the whole 8K word address space is directly
accessed. Most AVR instructions have a single 16-bit word format. Every program
memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section (256
to 2,048 bytes, see page 134) and the Application Program section. Both sections have
dedicated Lock bits for write and read/write protection. The SPM instruction that writes
into the Application Flash memory section is allowed only in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM, and
consequently the Stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The 11-bit Stack Pointer SP is read/write accessible in the
I/O space.
8 ATmega163(L)
1142E–AVR–02/03
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