ATmega163(L)
The 1,024 bytes data SRAM can be easily accessed through the five different address-
ing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its Control Registers in the I/O space with an additional
Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt
Vector in the Interrupt Vector table at the beginning of the Program memory. The inter-
rupts have priority in accordance with their Interrupt Vector position. The lower the
Interrupt Vector address, the higher the priority.
Figure 6. Memory Maps
Program Memory
$0000
Application Flash Section
Boot Flash Section
$1FFF
9
1142E–AVR–02/03