ATTINY22 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATTINY22 Datasheet PDF : 59 Pages
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Figure 2. External Clock Drive Configuration
PB3
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access
time. This means that during one single clock cycle, one arithmetic logic unit (ALU) operation is executed. Two operands
are output from the register file, the operation is executed, and the result is stored back in the register file in one clock
cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing enabling
efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table
look up function. These added function registers are the 16-bit X-register, Y-register and Z-register.
Figure 3. The ATtiny22/L AVR RISC Architecture
AVR ATtiny22/L Architecture
Data Bus 8-bit
1K x 16
Program
Flash
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Status
and Test
32 x 8
General
Purpose
Registers
ALU
Control
Registers
Interrupt
Unit
SPI
Unit
8-bit
Timer/Counter
Watchdog
Timer
128 x 8
Data
SRAM
I/O Lines
128 x 8
EEPROM
4
ATtiny22/22L
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