ATtiny22L
External Reset
An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even
if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the
Reset Threshold Voltage - VRST - on its positive edge, the delay timer starts the MCU after the Time-out period tTOUT has
expired.
Figure 24. External Reset During Operation
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of 1 clock cycle duration. On the falling edge of this pulse,
the delay timer starts counting the Time-out period tTOUT. Refer to page 28 for details on operation of the Watchdog.
Figure 25. Watchdog Reset During Operation
21