ATV2500B View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATV2500B Datasheet PDF : 21 Pages
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AC Characteristics
Symbol
tPD1
tPD2
tPD3
tPD4
tEA1
tER1
tEA2
tER2
tAW
tAP
tAPF
Parameter
Input to Non-registered Output
Feedback to Non-registered
Output
Input to Non-registered Feedback
Feedback to Non-registered
Feedback
Input to Output Enable
Input to Output Disable
Feedback to Output Enable
Feedback to Output Disable
Asynchronous Reset Width
Asynchronous Reset to
Registered Output
Asynchronous Reset to
Registered Feedback
-12
Min Max
12
-15
Min Max
15
-20
Min Max
20
-25
Min Max
25
-30
Min Max
30
Units
ns
12
15
20
25
30
ns
8
11
15
18
20
ns
8
11
15
18
20
ns
12
15
20
25
30
ns
12
15
20
25
30
ns
12
15
20
25
30
ns
12
15
20
25
30
ns
6
8
12
15
18
ns
15
18
22
28
30
ns
12
15
19
25
30
ns
Input Test Waveforms and
Measurement Levels
Output Test Load
Preload and Observability of Registered Outputs
The ATV2500Bs registers are provided with circuitry to
allow loading of each register asynchronously with either a
high or a low. This feature will simplify testing since any
state can be forced into the registers to control test
sequencing. A VIH level on the odd I/O pins will force the
appropriate register high; a VIL will force it low, independent
of the polarity or other configuration bit settings.
The PRELOAD state is entered by placing an 10.25V to
10.75V signal on SMP lead 42. When the preload clock
SMP lead 23 is pulsed high, the data on the I/O pins is
placed into the 12 registers chosen by the Q select and
even/odd select pins.
Register 2 observability mode is entered by placing an
10.25V to 10.75V signal on pin/lead 2. In this mode, the
contents of the buried register bank will appear on the
associated outputs when the OE control signals are active.
10
ATV2500B(Q)(L)
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