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ATTINY261-15MAZ View Datasheet(PDF) - Atmel Corporation

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ATTINY261-15MAZ Datasheet PDF : 227 Pages
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2. Overview
The ATtiny261/461/861 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny261/461/861 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
Watchdog
Timer
Watchdog
Oscillator
Oscillator
Circuits /
Clock
Generation
EEPROM
Power
Supervision
POR / BOD &
RESET
Flash
debugWIRE
PROGRAM
LOGIC
SRAM
CPU
Timer/Counter0
Timer/Counter1
A/D Conv.
USI
Analog Comp.
Internal
Bandgap
AVCC
AGND
AREF
3
11
PORT B (8)
PORT A (8)
PB[0..7]
PA[0..7]
RESET
XTAL[1..2]
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
4 ATtiny261/ATtiny461/ATtiny861
7753C–AVR–07/09

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