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ATTINY85V-10MUR View Datasheet(PDF) - Atmel Corporation

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ATTINY85V-10MUR Datasheet PDF : 29 Pages
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2. Overview
The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1
MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
8-BIT DATABUS
PROGRAM
COUNTER
VCC
PROGRAM
FLASH
GND
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
PROGRAMMING
LOGIC
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
WATCHDOG
TIMER
MCU CONTROL
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTER0
TIMER/
COUNTER1
UNIVERSAL
SERIAL
INTERFACE
INTERRUPT
UNIT
DATA
EEPROM
CALIBRATED
INTERNAL
OSCILLATOR
TIMING AND
CONTROL
OSCILLATORS
DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
PORT B DRIVERS
ADC /
ANALOG COMPARATOR
RESET
PB[0:5]
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
ATtiny25/45/85 [DATASHEET]
4
2586PS–AVR–06/2013

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