ATTINY87-MU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATTINY87-MU

8-bit Microcontroller with 8K/16K Bytes In-System Programmable Flash and LIN Controller

Atmel Corporation 

ATtiny87/ATtiny167

Figure 3-2. Data Memory Map

Data Memory

32 Registers

64 I/O Registers

160 Ext I/O Reg.

0x0000 - 0x001F

0x0020 - 0x005F

0x0060 - 0x00FF

ISRAM start

Internal SRAM

(ISRAM size)

3.2.1

ISRAM end

Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clkCPU cycles as described in Figure 3-3.

Figure 3-3. On-chip Data SRAM Access Cycles

T1

T2

T3

clk

CPU

Address

Data

WR

Data

RD

Compute Address

Address valid

Memory Access Instruction

Next Instruction

3.3 EEPROM Data Memory

The ATtiny87/167 contains EEPROM memory (see “E2 size” in Table 3-1 on page 15). It is

organized as a separate data space, in which single bytes can be read and written. The

EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the

EEPROM and the CPU is described in the following, specifying the EEPROM Address Regis-

ters, the EEPROM Data Register and the EEPROM Control Register.

Section 21. “Memory Programming” on page 225 contains a detailed description on EEPROM

programming in SPI or Parallel Programming mode.

17

8265A–AVR–08/10

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