ATV750B View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATV750B Datasheet PDF : 16 Pages
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ATV750B
Preload of Registered Outputs
The ATV750B’s registers are provided with circuitry to
allow loading of each register asynchronously with either a
high or a low. This feature will simplify testing since any
state can be forced into the registers to control test
sequencing. A VIH level on the I/O pin will force the register
high; a VIL will force it low, independent of the output polar-
ity. The PRELOAD state is entered by placing a 10.25V to
10.75V signal on pin 8 on DIPs, and lead 10 on SMDs.
When the clock term is pulsed high, the data on the I/O
pins is placed into the register chosen by the Select Pin.
Level forced on registered
output pin during PRELOAD cycle
VIH
VIL
VIH
VIL
Select Pin State
Low
Low
High
High
Register #0 State after cycle
High
Low
X
X
Register #1 State after cycle
X
X
High
Low
Power Up Reset
The registers in the ATV750Bs are designed to reset during
power up. At a point delayed slightly from VCC crossing
VRST, all registers will be reset to the low state. The output
state will depend on the polarity of the output buffer.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock terms or
pin high, and
3. The clock pin, or signals from which clock terms are
derived, must remain stable during tPR.
Parameter Description
Typ Max Units
tPR
VRST
Power-Up Reset Time 600 1000 ns
Power-Up Reset Voltage 3.8 4.5
V
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
Max
CIN
COUT
5
8
6
8
Units
pF
pF
Conditions
VIN = 0V
VOUT = 0V
9
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