HSP48901JC-30(2004) View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

HSP48901JC-30
(Rev.:2004)

3 x 3 Image Filter

Intersil 

Pinouts

HSP48901

68 LEAD PLCC

TOP VIEW

DIN2 (7)

DIN2 (6)

DIN2 (5)

DIN2 (4)

DIN2 (3)

DIN2 (2)

DIN2 (1)

DIN2 (0)

GND

DIN3 (7)

DIN3 (6)

DIN3 (5)

DIN3 (4)

DIN3 (3)

DIN3 2)

DIN3 (1)

DIN3 (0)

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

10

60

11

59

12

58

13

57

14

56

15

55

16

54

17

53

18

52

19

51

20

50

21

49

22

48

23

47

24

46

25

45

26

44

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

DOUT6

DOUT7

DOUT8

DOUT9

GND

DOUT10

DOUT11

DOUT12

DOUT13

DOUT14

DOUT15

DOUT16

DOUT17

DOUT18

DOUT19

VCC

FRAMES

Pin Descriptions

NAME PLCC PIN TYPE

DESCRIPTION

VCC

9, 27, 45, 61

The +5V power supply pins. 0.1µF capacitors between the VCC and GND pins are

recommended.

GND 18, 29, 38, 56

The device ground.

CLK

28

I Input and System clock. Operations are synchronous with the rising edge of this clock signal.

DIN1(7-0)

1-8

I Pixel Data Input Bus #1. These inputs are used to provide 8-bit pixel data to the HSP48901. The data must be

provided in a synchronous fashion, and is latched on the rising edge of the CLK signal. The DIN1(0-7) inputs

are also used to input data when operating in the 9-Tap FIR mode.

DIN2(7-0)

10-17

I Pixel Data Input Bus #2. Same as above. These inputs should be grounded when operating in the 1D mode.

DIN3(7-0)

19-26

I Pixel Data Input Bus #3. Same as above. These inputs should be grounded when operating in the 1D mode.

CIN7-0

30-37

I Coefficient Data Input Bus. This input bus is used to load the Coefficient Mask Register(s) and the Initialization

Register. The register to be loaded is defined by the register address bits A0-2. The CIN0-7 data is loaded to

the addressed register through the use of the LD input.

DOUT19-0 46-55, 57-60, O Output Data Bus. This 20-Bit output port is used to provide the convolution result. The result is the sum of

62-67

products of the input data samples and their corresponding coefficients.

FRAME

44

I FRAME is an asynchronous new frame or vertical sync input. A low on this input resets all internal circuitry

except for the Coefficient and INT Registers. Thus, after a FRAME reset has occurred, a new frame of pixels

may be convolved without reloading these registers.

HOLD

40

I The Hold Input is used to gate the clock from all of the internal circuitry of the HSP48901. This signal is

synchronous, is sampled on the rising edge of CLK and takes effect on the following cycle. While this signal is

active (high), the clock will have no effect on the HSP48901 and internal data will remain undisturbed.

A2-0

41-43

I Control Register Address. These lines are decoded to determine which register in the control logic is the

destination for the data on the CIN0-7 inputs. Register loading is controlled by the A0-2 and LD inputs.

LD

39

I Load Strobe. LD is used for loading the Internal Registers of the HSP48901. The rising edge of LD will latch

the CIN0-7 data into the register specified by A0-2. The Address on A0-2 must be setup with respect to the

falling edge of LD and must be held with respect to the rising edge of LD.

2

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