SAA7201 View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
SAA7201 Datasheet PDF : 36 Pages
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Philips Semiconductors
Integrated MPEG2 AVG decoder
Objective specification
SAA7201
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V_STROBE
A_STROBE
video bit (n + 6)
≥25 ns
≥25 ns
≥50 ns
video bit (n + 7)
Fig.4 Timing diagram of serial input mode.
audio bit (m + 0)
first bit of a byte
MGD324
Alternatively data can be received in a 1-bit serial format at
rates up to 20 Mbit/s. In this mode, data is input at the LSB
input of the AV_DATA bus. Audio and video data must be
input in multiples of 8 bits. The first bit after switching from
audio to video (or the other way around) must be the first
bit of a byte since this transition will be used for the internal
bit-to-byte conversion.
Audio/video data can also be received via the CPU
interface in 8 or 16-bit mode. The peak rate is 27 Mbytes/s
in bursts of ≤128 bytes with a sustained rate up to
9 Mbytes/s. However, the MPEG bit rate is still limited to
15 Mbit/s for video and 448 kbit/s for audio.
Independent of the input mode all audio and video input
data are stored sequentially in the audio or video input
buffer area of the external memory. The audio and video
data can be either in MPEG2 PES, MPEG1 packet or ES
format.
Memory interface unit
The memory interface takes care of addressing and
control of the 16-Mbit external SDRAM. The SDRAM
should be either JEDEC compliant either the ‘lite/PC’
version.
Due to memory communication requirements this interface
runs at 81 MHz. The SDRAM types used with the
SAA7201 should be organized as 1M × 16, split internally
in two banks, each having 2048 pages of 256 words of
16 bits.
The target SDRAM type is NEC µPD 4516161G5-A12-7FJ
(83 MHz JEDEC version) or NEC
µPD 4516421G5-A83-7FJ-PC (83 Mhz PC version).
Clock generation
The clock generation unit generates all the internal
processing clocks, the clock for the system time base
counter and the audio oversampling clock for the audio
DAC. For this purpose a non-integer divider plus a PLL is
implemented. In order to get reliable audio and video
decoding the 27 MHz input clock should be locked
externally to the MPEG time base.
Host interface system
The host interface system handles the communication
between on one side the SAA7201 plus SDRAM and on
the other side the external CPU. The interface consists of
a 16-bit wide data bus plus 8 address lines. It is compatible
with both Motorola’s 68xxx and Intel’s x86 family.
An optimized interface with the SAA7208 is also
supported. Via this interface a fast direct access to a large
number of internal status and data registers can be
achieved. Moreover, the external SDRAM can be
accessed via a specific register in combination with an
internally implemented auto increment counter.
The access to the external SDRAM is guaranteed up to a
sustained data rate of 9 Mbyte per second. However, in
practice the achievable data rate can be much higher.
Next to the data and address lines, 4 interrupt lines are
part of the host interface bus. Each interrupt line can
monitor up to 32 internal events which all can be masked
individually. Examples of internal events are audio/video
bit stream information, decoder status, internal error
conditions and input buffer occupation. The latter may be
very useful in interactive applications to serve as input data
request line.
1997 Jan 29
12
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