FUNCTIONAL DESCRIPTION
Functional Overview
Bt819A/7A/5A
eo controller to do away with pins required for the corresponding video control
signals.
In the API mode, the Bt819A outputs only the active pixels and control codes at
a rate asynchronous with the sample clock. A 40-pixel-deep FIFO buffers the pixel
output port and enables the system to burst pixels out of the Bt819A at rates up to
35 Mpixels/sec. An input clock must be provided on CLKIN for operation in this
mode. The Bt819A outputs the DVALID, AEF and AFF flags to provide the system
information on the status of the FIFO.
I2C Interface
The Bt819A/7A/5A registers are accessed via a two-wire Inter-Integrated Circuit
(I2C) interface. The Bt819A/7A/5A operates as a slave device. Serial clock and
data lines, SCL and SDA, are used to transfer data from the bus master at a rate of
100 Kbits/s. Chip select and reset signals are also available to select one of two
possible Bt819A/7A/5A devices in the same system and to set the registers to their
default values.
4