CY7C1324-80AC(1999) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1324-80AC Datasheet PDF : 15 Pages
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CY7C1324
3.3V 128K x 18 Synchronous
Cache RAM
Features
Functional Description
• Supports 117-MHz microprocessor cache systems with
zero wait states
• 128K by 18 common I/O
• Fast clock-to-output times
— 7.5 ns (117 MHz)
• Two-bit wrap-around counter supporting either inter-
leaved or linear burst sequence
• Separate processor and controller address strobes pro-
vides direct interface with the processor and external
cache controller
• Synchronous self-timed write
• Asynchronous output enable
• I/Os capable of 2.5–3.3V operation
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ “sleep” mode
The CY7C1324 is a 3.3V, 128K by 18 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-
tures the first address in a burst and increments the address
automatically for the rest of the burst access.
The CY7C1324 allows both interleaved or linear burst se-
quences, selected by the MODE input pin. A HIGH input on
MODE selects an interleaved burst sequence, while a LOW
selects a linear burst sequence. Burst accesses can be initiat-
ed with the Processor Address Strobe (ADSP) or the cache
Controller Address Strobe (ADSC) inputs. Address advance-
ment is controlled by the Address Advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A[16:0]
17
GW
BWE
BW 1
BW 0
CE1
CE2
CE3
MODE
(A0,A1) 2
BURST Q0
CE COUNTER
CLR
Q1
Q
ADDRESS
15
CE
D
REGISTER
15
D DQ[15:8] Q
BYTEWRITE
REGISTERS
D DQ[7:0] Q
BYTEWRITE
REGISTERS
D
CE
ENABLE
REGISTER
Q
CLK
17
128K X 18
MEMORY
ARRAY
18
18
OE
ZZ
SLEEP
CONTROL
Pin
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Pentium is a registered trademark of Intel Corporation.
7C1324–117
7.5
350
1.0
7C1324–100
8.0
325
1.0
7C1324–80
8.5
300
1.0
INPUT
REGISTERS
CLK
DQ[15:0]
DP[1:0]
7C1324–50
11.0
250
1.0
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 4, 1999
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