Multimedia ICs
3. Slave mode, single clock mode
Encoder slave (pin 33 = L)
Internal clock = input clock (pin 53 = L)
BU1424K
VCLK (53pin)
BCLK
(Internal clock)
Input data
output data
(HSY, VSY)
Tds3
Tsh1 Tsd1
Fig.13
∗ In this mode, the internal clock (BCLK) begins to operate at the same phase as the VCLK input, following the rise
of the RSTB pin (pin 52).
Table 13
Parameter
Data setup time 3
Sync signal hold time
Sync signal hold time
Symbol
Min.
Typ.
Max.
Tds3
10
—
—
Tsh1
10
—
—
Tsd1
10
—
—
4. Slave mode, doubled clock mode
Encoder slave (pin 33 = L)
Internal clock = 2 ∗ input clock (pin 53 = L)
VCLK (53pin)
BCLK
(Internal clock)
Input data
Input data
(HSY, VSY)
Tds4
Tsh2 Tsd2
Fig.14
20