C8051F326/7
Figure 13.2. UART0 Timing Without Parity or Extra Bit.......................................... 120
Figure 13.3. UART0 Timing With Parity ................................................................. 120
Figure 13.4. UART0 Timing With Extra Bit ............................................................. 120
Figure 13.5. Typical UART Interconnect Diagram.................................................. 121
Figure 13.6. UART Multi-Processor Mode Interconnect Diagram .......................... 122
14. Timers
Figure 14.1. T0 Mode 0 Block Diagram.................................................................. 128
Figure 14.2. T0 Mode 2 Block Diagram.................................................................. 129
Figure 14.3. T0 Mode 3 Block Diagram.................................................................. 130
15. C2 Interface
Figure 15.1. Typical C2 Pin Sharing....................................................................... 137
8
Rev. 1.1