C8051F912 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F912

Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU

Silicon Laboratories 

C8051F91x-C8051F90x

List of Figures

Figure 1.1. C8051F912 Block Diagram .................................................................... 18

Figure 1.2. C8051F911 Block Diagram .................................................................... 18

Figure 1.3. C8051F902 Block Diagram .................................................................... 19

Figure 1.4. C8051F901 Block Diagram .................................................................... 19

Figure 1.5. Port I/O Functional Block Diagram ......................................................... 21

Figure 1.6. PCA Block Diagram................................................................................ 22

Figure 1.7. ADC0 Functional Block Diagram............................................................ 23

Figure 1.8. ADC0 Multiplexer Block Diagram ........................................................... 24

Figure 1.9. Comparator 0 Functional Block Diagram ............................................... 25

Figure 1.10. Comparator 1 Functional Block Diagram ............................................. 25

Figure 3.1. QFN-24 Pinout Diagram (Top View) ...................................................... 30

Figure 3.2. QSOP-24 Pinout Diagram F912 (Top View) .......................................... 31

Figure 3.3. QFN-24 Package Drawing ..................................................................... 32

Figure 3.4. Typical QFN-24 Landing Diagram.......................................................... 33

Figure 3.5. QSOP-24 Package Diagram .................................................................. 34

Figure 3.6. QSOP-24 Landing Diagram ................................................................... 35

Figure 4.1. Active Mode Current (External CMOS Clock) ........................................ 41

Figure 4.2. Idle Mode Current (External CMOS Clock) ............................................ 42

Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V) ... 43

Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V) ... 44

Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V).... 45

Figure 4.6. Typical One-Cell Suspend Mode Current............................................... 46

Figure 4.7. Typical VOH Curves, 1.8–3.6 V ............................................................. 48

Figure 4.8. Typical VOH Curves, 0.9–1.8 V ............................................................. 49

Figure 4.9. Typical VOL Curves, 1.8–3.6 V .............................................................. 50

Figure 4.10. Typical VOL Curves, 0.9–1.8 V ............................................................ 51

Figure 5.1. ADC0 Functional Block Diagram............................................................ 61

Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0).... 64

Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 ................... 65

Figure 5.4. ADC0 Equivalent Input Circuits .............................................................. 66

Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data ... 77

Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data...... 77

Figure 5.7. ADC0 Multiplexer Block Diagram ........................................................... 78

Figure 5.8. Temperature Sensor Transfer Function ................................................. 80

Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.68 V) ..... 81

Figure 5.10. Voltage Reference Functional Block Diagram...................................... 83

Figure 7.1. Comparator 0 Functional Block Diagram ............................................... 88

Figure 7.2. Comparator 1 Functional Block Diagram ............................................... 89

Figure 7.3. Comparator Hysteresis Plot ................................................................... 90

Figure 7.4. CPn Multiplexer Block Diagram.............................................................. 95

Figure 8.1. CIP-51 Block Diagram............................................................................ 98

Figure 9.1. C8051F91x-C8051F90x Memory Map ................................................. 107

Figure 9.2. Flash Program Memory Map................................................................ 108

Rev. 1.0

9

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