CAT25C08LA View Datasheet(PDF) - Catalyst Semiconductor => Onsemi
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CAT25C08LA Datasheet PDF : 16 Pages
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CAT25C08/16
DESIGN CONSIDERATIONS
The CAT25C08/16 powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued to perform any writes to the device after
power up. Also,on power up CS should be brought low
to enter a ready state and receive an instruction. After
a successful byte/page write or status register write, the
CAT25C08/16 goes into a write disable mode. CS must
be set high after the proper number of clock cycles to
start an internal write cycle. Access to the array during
an internal write cycle is ignored and programming is
continued. On power up, SO is in a high impedance. If
an invalid op code is received, no data will be shifted
into the CAT25C08/16, and the serial output pin (SO)
will remain in a high impedance state until the falling
edge of CS is detected again.
When powering down, the supply should be taken down
to 0V, so that the CAT25C08/16 will be reset when
power is ramped back up. If this is not possible, then,
following a brown-out episode, the CAT25C08/16 can
be reset by refreshing the contents of the Status Reg-
ister (See Application Note AN10).
Figure 7. WRSR Timing
CS
SCK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
OPCODE
SI
0
0
0
0
00
0
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) – – – – –
DATA IN
1
7
6
5
4
3
2
10
MSB
Figure 8. Page Write Instruction Timing
CS
SCK
SI
012345678
21 22 23 24-31 32-39 24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
OPCODE
00 00 00
BYTE ADDRESS*
DATA IN
1 0 AN
Data Data Data
A0 Byte 1 Byte 2 Byte 3
Data Byte N
7..1
0
SO
*Please check the Byte Address Table.
Note: Dashed Line= mode (1, 1) – – – – –
HIGH IMPEDANCE
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. 1016, Rev. C
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