CAT93C46LIG View Datasheet(PDF) - ON Semiconductor

Part Name

Description

Manufacturer

CAT93C46LIG

1 Kb Microwire Serial EEPROM

ON Semiconductor 

CAT93C46

Write

After receiving a WRITE command (Figure 5), address

and the data, the CS (Chip Select) pin must be deselected for

a minimum of tCSMIN. The falling edge of CS will start the

self clocking for auto−clear and data store cycles on the

memory location specified in the instruction. The clocking

of the SK pin is not necessary after the device has entered the

self clocking mode. The ready/busy status of the CAT93C46

can be determined by selecting the device and polling the

DO pin. Since this device features Auto−Clear before write,

it is NOT necessary to erase a memory location before it is

written into.

Erase

Upon receiving an ERASE command and address, the CS

(Chip Select) pin must be de−asserted for a minimum of

tCSMIN (Figure 6). The falling edge of CS will start the self

clocking clear cycle of the selected memory location. The

clocking of the SK pin is not necessary after the device has

entered the self clocking mode. The ready/busy status of the

CAT93C46 can be determined by selecting the device and

polling the DO pin. Once cleared, the content of a cleared

location returns to a logical “1” state.

Erase All

Upon receiving an ERAL command (Figure 7), the CS

(Chip Select) pin must be deselected for a minimum of

tCSMIN. The falling edge of CS will start the self clocking

clear cycle of all memory locations in the device. The

clocking of the SK pin is not necessary after the device has

entered the self clocking mode. The ready/busy status of the

CAT93C46 can be determined by selecting the device and

polling the DO pin. Once cleared, the contents of all memory

bits return to a logical “1” state.

Write All

Upon receiving a WRAL command and data, the CS

(Chip Select) pin must be deselected for a minimum of

tCSMIN (Figure 8). The falling edge of CS will start the self

clocking data write to all memory locations in the device.

The clocking of the SK pin is not necessary after the device

has entered the self clocking mode. The ready/busy status of

the CAT93C46 can be determined by selecting the device

and polling the DO pin. It is not necessary for all memory

locations to be cleared before the WRAL command is

executed.

SK

tCSMIN

CS

AN AN−1

DI

101

A0 DN

D0

STATUS

VERIFY

STANDBY

tSV

tHZ

HIGH−Z

DO

READY

HIGH−Z

BUSY

tEW

Figure 5. Write Instruction Timing

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