MAX3750CEE View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX3750CEE Datasheet PDF : 6 Pages
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+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs
_________________Circuit Description
A simplified block diagram of the single port bypass is
shown in Figure 1. IN+ and IN- drive an input buffer
(INBUFF) with 150Ω of internal differential input termi-
nation. INBUFF drives an output buffer (LOBUFF) and
an input to a multiplexer (MUX).
A low TTL input at SEL selects the signal path of
INBUFF through MUX to the output buffer (OUTBUFF).
When SEL has a high TTL logic level present the signal
path is into LIBUFF, through MUX, to OUTBUFF.
Low-Frequency Cutoff
The low-frequency cutoff is determined by the input
resistance and the coupling capacitor as illustrated by
the following equation:
fC = 1 / (2πRC)
In a typical system where R = 150Ω and C = 100nF,
resulting in fC = 10kHz.
Layout Techniques
The MAX3750/MAX3751 are high-frequency products.
The performance of the circuit is largely dependent
upon layout of the circuit board. Use a multilayer circuit
board with dedicated ground and VCC planes. Power
supplies should be capacitively bypassed to the
ground plane with surface-mount capacitors placed
near the power-supply pins.
LOBUFF
IN+
INBUFF
IN-
MAX3750
MAX3751
LIBUFF
MUX
D0 Q
D1
SEL
TTLIN
OUTBUFF
OUT+
OUT-
VCC
GND
SEL
NOTE: SEE INTERNAL INPUT/OUTPUT SCHEMATICS FOR DETAILED TERMINATIONS (FIGURES 2–5).
Figure 1. MAX3750/MAX3751 Block Diagram
4 _______________________________________________________________________________________
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