CDB5321 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CDB5321 Datasheet PDF : 12 Pages
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CDB5321
ON* Do not use offset register
USEOR
OFF Use offset register
ON* Disable offset register calibration
ORCAL
OFF Enable offset register calibration
ON Sets SID to Logic 0
SID
OFF* Allows pull-up on SID line
ERR
ON Sets ERR to logic 0
OFF* Allows CS5322 ERROR output
RSEL
ON Select status register
OFF* Select conversion data register
ON* Chip select active
CS
OFF Chip select inactive
ON Enables write mode via SID pin
R/W
OFF* Enables read mode via SOD pin
OFF = OPEN = 1
*Default to use Figure 6 interface.
DECA
DECB
DECC
ABC Output Word Rate
000
62.5
Selection 1 0 0
125
via hardware 0 1 0
250
pins
110
500
001
1000
101
2000
011
4000
PWDN
H/S
CSEL
TDATA
ON* Normal Operation
OFF Power down active
ON
Selects configuration register for
operating mode
OFF*
Select hardware pins for operating
mode
ON* Selects MDATA from modulator
OFF Selects TDATA as filter input
ON* Sets TDATA input to logic 0
OFF Enables TDATA from J1 header
OFF = OPEN = 1
*Default to use Figure 6 interface.
Table 1. S3 DIP Switch Selections
Table 2. S4 DIP switch selections
From
Figure
4
+5V
U4D
9 14 8
DRDY
U4
SCLK 13
12
U4F
SOD 11
10
7 U4E
10
R4
0.1
C35
5
1
3
+ 10 µF
C5
U4C
6
U4A 2
U4B 4
DRDY
SCLK
SOD
JP6
+5V
+5V
DRDY
SCLK
SOD
U3, U4 = 74HC04
5
6
U3C
13
12
U3F
11
10
U3D
9
8
U3E
Figure 5. Serial Latch Interface on CDB5321 (Rev B) board
20
DS88DB2
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