CDB5360 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CDB5360

Evaluation Board for CS5334/CS5335/CS5360

Cirrus Logic 

CDB5334/35/60

circuit. The analog input connector is a standard fe-

male XLR with Pin 2 positive, Pin 3 return, and Pin

1 shield.

R1, R5, and C8 form an RC network which pro-

vides anti-alias filtering and the optimum source

impedance for the CS5334, CS5335, or CS5360

right channel inputs. R2, R3, and C42 duplicate this

function for the left channel.

Space has been left on the evaluation board for in-

put protection diodes D1-D4 on the right channel,

and D8-D11 on the left channel, shown in Figure 3.

These diodes are optional as the CS5334, CS5335,

and CS5360 are able to withstand input currents of

100mA maximum, as stated in the

CS5334/CS5335 and CS5360 data sheets. The out-

put current from the op-amp used in the analog fil-

ter on the evaluation board is not able to deliver a

current that exceeds 100mA. Input protection di-

odes are recommended if there is a possibility that

over-range signals could be applied at the ADC in-

puts which exceed this level. See the application

note, "A/D Converter Input Protection Techniques"

in the 1994 Crystal Semiconductor Audio Da-

tabook.

CS5334, CS5335, and CS5360 A/D

Converters

The CS5334, CS5335, and CS5360 A/D converters

are shown in Figure 4. A description of these devic-

es are included in the CS5334/CS5335 and CS5360

data sheets.

CS8402A Digital Audio Interface

Figure 5 shows the circuitry for the CS8402A dig-

ital audio interface transmitter. The CS8402A can

implement AES/EBU, S/PDIF, and EIAJ-340 in-

terface standards. The Digital Interface Format

(DIF) for the transmitter is set automatically to

match the format chosen for the CS5334, CS5335,

or CS5360 (the DIF is selected by the DIF1 and

DIF0 switches on SW1, as defined in Table 3).

SW2 provides 8 DIP switches to select various

modes and bits for the CS8402A; switch defini-

tions and the default settings for SW2 are listed in

Tables 4 and 5. Digital outputs are provided on an

RCA connector via isolation transformer and on an

optical transmitter. For more detailed information

on the CS8402A and the digital audio standards,

see the CS8401A/CS8402A data sheet.

Serial Output Interface

A serial output interface is provided on HDR2, as

shown in Figure 6. When the SMODE1 and

SMODE2 jumpers, defined in Table 2, are set to

the MASTER position, MCLK, SCLK, LRCK,

SDATA, and FRAME signals are outputs. When

the SMODE1 and SMODE2 jumpers are in the

SLAVE position, MCLK, SDATA, and FRAME

are outputs, while SCLK and LRCK become in-

puts. Hence, in SLAVE mode, the SCLK and

LRCK signals must be externally derived from

MCLK to run the ADC. All signals are buffered in

order to isolate the converter from external circuit-

ry. Signal buffering is provided by a 74HCT243

transceiver (U10) and a 74HCT541 buffer (U11).

ALTERA PLD AND PEAK SIGNAL

LEVEL LEDS

The Altera EPM7128 programmable logic device

(PLD), shown in Figure 8, is designed to support

three major features on the evaluation board. First,

it automatically configures the CS8402A transmit-

ter to accept the Digital Interface Format chosen for

the CS5334, CS5335, or CS5360. Second, the PLD

provides a 128x Fs master clock for the CS8402A.

Third, it decodes and updates the Peak Signal Level

(PSL) bits which give information about the ampli-

tude of the input signal.

CS8402A Format Configuration

The CS5334, CS5335, and CS5360 support three

Digital Interface Formats for both master and slave

configurations. Format 0 has valid data on the ris-

ing edge of SCLK. The CS8402A transmitter has

no corresponding mode which matches Format 0,

DS194DB3

3

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