CDB5396 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CDB5396

120 dB, 96 kHz Audio A/D Converter

Cirrus Logic 

CS5396 CS5397

the analog buffer stage and the CS5396/97 analog

modulator. The high pass filter can be defeated

with the control register. It is also possible to write

to the left/right offset registers to establish a prede-

termined offset.

The characteristics of this first-order high pass fil-

ter are outlined below for Fs equal to 48 kHz. The

filter response scales linearly with sample rate.

Frequency response: -3 dB @ 1.8 Hz

-0.036 dB @ 20 Hz

Phase deviation: 5.3 degrees @ 20 Hz

Passband ripple: None

Input Level Monitoring - Control Port Mode

The CS5396/97 includes independent Peak Input

Level Monitoring for each channel. The analog-to-

digital converter continually monitors the peak dig-

ital signal for both channels and records these val-

ues in the Active registers. This information can be

transferred to the Output registers by writing the

PU (Peak Update) bit which will also reset the Ac-

tive register. The Active register contains the peak

signal level since the previous peak update request.

The 8-bit contents of the output registers are avail-

able in both interface modes. The peak signal level

information is available in two formats - High Res-

olution Mode and Bar Graph Mode. The output for-

mat is controlled via the control register.

High Resolution Mode

Bits P7-P0 indicate the Peak Signal Level (PSL)

since the previous peak update (or previous write of

the PU bit). If the ADC input level is less than full-

scale, bits P5-P0 represent the peak value from -

60 dB to 0 dB of full scale in 1 dB steps. The PSL

outputs are accurate to within 0.25 dB. Bit P6 pro-

vides a coarse means of determining an ADC input

idle condition. Bit P7 indicates an ADC overflow

condition if the ADC input level is greater than

full-scale.

P7 - Overrange

0 - Analog input less than full-scale level

1 - Analog input greater than full-scale

P6 - Idle channel

0 - Analog input >-60 dB from full-scale

1 - Analog input <-60 dB from full-scale

P5 to P0 - Input Level Bits (1 dB steps)

Inputs <0 dB P5 - P0

0 dB

000000

-1 dB

000001

-2 dB

000010

-60 dB

111100

Bar Graph Mode

This mode provides a decoded output format which

indicates the peak input signal level in a “Bar

Graph” format which can be used to drive front

panel LEDs. This decoded output can be used to

drive front panel LEDs.

Input Level

Overflow

0 dB to -3 dB

-3 dB to -6 dB

-6 dB to -10 dB

-10 dB to -20 dB

-20 dB to -30 dB

-30 dB to -40 dB

-40 dB to -60 dB

< - 60 dB

T7 - T0

11111111

01111111

00111111

00011111

00001111

00000111

00000011

00000001

00000000

Dual Digital Audio Outputs

The CS5396/97 contains two stereo digital audio

output channels - SDATA1 and SDATA2. These

audio output channels are completely independent,

as SDATA1 can contain 24-bit audio data simulta-

neous with psychoacoustic audio data on SDATA2.

Another example of this independence is 24-bit au-

dio data output on SDATA1 simultaneously with a

low group delay output on SDATA2.

The audio output formats are completely program-

mable through the I2C/SPI µC interface. The output

18

DS229PP2

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