CDP1802BCQ View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
CDP1802BCQ Datasheet PDF : 28 Pages
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CDP1802A, CDP1802AC, CDP1802BC
Performance Curves (Continued)
TA = -40oC TO +85oC
20
10
VGS, GATE-TO-SOURCE = 5V
5
0
1
2
3
4
5
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
FIGURE 21. CDP1802BC MINIMUM OUTPUT LOW (SINK)
CURRENT CHARACTERISTICS
1000 TA = 25oC
100
150
TA = 25oC
125
VCC = VDD = 5V
100
∆tPLH
75
50 ∆tPHL
VCC = VDD = 10V
VCC = VDD = 5V
25
VCC = VDD = 10V
0
25
50
100
150
200
∆CL, ∆ LOAD CAPACITANCE (pF)
NOTE: ANY OUTPUT EXCEPT XTAL
FIGURE 22. TYPICAL CHANGE IN PROPAGATION DELAY AS A
FUNCTION OF A CHANGE IN LOAD CAPACITANCE
FOR ALL TYPES
VCC = VDD = 10V
10 BRANCH
IDLE
1
VCC = VDD = 5V
0.1
0.01
0.1
1
10
fCL, CLOCK INPUT FREQUENCY (MHz)
NOTE: IDLE = “00” AT M(0000), BRANCH = “3707” AT M(8107), CL = 50pF
FIGURE 23. TYPICAL POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY FOR BRANCH INSTRUCTION AND IDLE
INSTRUCTION FOR ALL TYPES
Signal Descriptions
Bus 0 to Bus 7 (Data Bus)
8-bit bidirectional DATA BUS lines. These lines are used for
transferring data between the memory, the microprocessor,
and I/O devices.
N0 to N2 (I/O Control Lines)
Activated by an I/O instruction to signal the I/O control logic of
a data transfer between memory and I/O interface. These
lines can be used to issue command codes or device selec-
tion codes to the I/O devices (independently or combined with
the memory byte on the data bus when an I/O instruction is
being executed). The N bits are low at all times except when
an I/O instruction is being executed. During this time their
state is the same as the corresponding bits in the N register.
The direction of data flow is defined in the I/O instruction by bit
N3 (internally) and is indicated by the level of the MRD signal.
MRD = VCC: Data from I/O to CPU and Memory
MRD = VSS: Data from Memory to I/O
EF1 to EF4 (4 Flags)
These inputs enable the I/O controllers to transfer status
information to the processor. The levels can be tested by the
conditional branch instructions. They can be used in con-
junction with the INTERRUPT request line to establish inter-
rupt priorities. These flags can also be used by I/O devices
to “call the attention” of the processor, in which case the pro-
gram must routinely test the status of these flag(s). The
flag(s) are sampled at the beginning of every S1 cycle.
3-19
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