CDP1802AC View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

CDP1802AC

CMOS 8-Bit Microprocessors

Intersil 

CDP1802A, CDP1802AC, CDP1802BC

loaded into D, and R(N) is incremented by 1.

S1 RESET

IDLE • DMA • INT

FORCE S1

(LONG BRANCH,

LONG SKIP, NOP, ETC.)

S1 INIT

DMA

DMA

DMA

S1 EXECUTE

DMA

DMA • IDLE • INT

INT • DMA

S2 DMA

DMA • INT

S0 FETCH

DMA

DMA

S3 INT

PRIORITY: FORCE S0, S1

DMA IN

DMA OUT

INT

INT • DMA

FIGURE 25. STATE TRANSITION DIAGRAM

INSTRUCTION

MEMORY REFERENCE

LOAD VIA N

LOAD ADVANCE

LOAD VIA X

LOAD VIA X AND ADVANCE

LOAD IMMEDIATE

STORE VIA N

STORE VIA X AND DECREMENT

REGISTER OPERATIONS

INCREMENT REG N

DECREMENT REG N

INCREMENT REG X

GET LOW REG N

PUT LOW REG N

GET HIGH REG N

PUT HIGH REG N

LOGIC OPERATIONS (Note 1)

OR

OR IMMEDIATE

TABLE 1. INSTRUCTION SUMMARY (SEE NOTES)

OP

MNEMONIC CODE

OPERATION

LDN

LDA

LDX

LDXA

LDl

STR

STXD

0N M(R(N)) → D; FOR N not 0

4N M(R(N)) → D; R(N) + 1 → R(N)

F0 M(R(X)) → D

72 M(R(X)) → D; R(X) + 1 → R(X)

F8 M(R(P)) → D; R(P) + 1 → R(P)

5N D → M(R(N))

73 D → M(R(X)); R(X) - 1 → R(X)

INC

DEC

IRX

GLO

PLO

GHl

PHI

1N R(N) + 1 → R(N)

2N R(N) - 1 → R(N)

60 R(X) + 1 → R(X)

8N R(N).0 → D

AN D → R(N).0

9N R(N).1 → D

BN D → R(N).1

OR

F1 M(R(X)) OR D → D

ORl

F9 M(R(P)) OR D → D; R(P) + 1 → R(P)

3-23

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