GS8170DW18C-333I View Datasheet(PDF) - Giga Semiconductor
Part Name
Description
Manufacturer
GS8170DW18C-333I Datasheet PDF : 36 Pages
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Preliminary
GS8170DW18/36/72C-333/300/250
Read Operations
Pipelined Read
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2,
and E3) are active, the write enable input signal (W) is deasserted high, and ADV is asserted low. The address presented to the
address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines
that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge
of clock the read data is allowed to propagate through the output register and onto the output pins.
Single Data Rate Pipelined Read
Read
Deselect
Read
Read
Read
CK
Address
A
XX
C
D
E
F
ADV
/E1
/W
DQ
QA
QC
QD
CQ
Key
Hi-Z
Access
Rev: 1.00d 6/2002
10/36
© 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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