COM20051 View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

COM20051

Integrated Microcontroller and Network Interface with Watchdog Timer and A/D Converter Interface

SMSC -> Microchip 

BASIC ARCHITECTURE

The COM20051+ consists of six functional

blocks: the 80C32 microcontroller core,

ARCNET network cell (includes 1K of buffer

RAM), programmable address decoder,

watchdog timer, A/D converter interface, and

programmable interrupt router. The internal

architecture of the COM20051+ is shown in

Figure 1.

external interrupt ports or can be assigned to

one of the general purpose I/O ports. The

ARCNET and data acquistion interrupts are

internally wire ANDed with the external interrupt

pin to allow greater system flexibility.

80C32 ARCHITECTURE AND INSTRUCTION

SET

The 80C32 microcontroller is a full ROMless

implementation of the popular Intel 8051 series.

The ARCNET network core is similar in

architecture to SMSC's popular COM20020

family of ARCNET controllers and retains the

same command and status flags of previous

ARCNET controllers. The programmable

address decoder maps the ARCNET registers,

watchdog timer, and data acquistion registers

into a 256-byte page anywhere within the

External Data Memory space of the 80C32. The

peripheral functions were mapped into the

External Data Memory space to simplify

software and application development and for

production test purposes. Access to the

peripheral functions during software

development is achieved by invoking the

Emulate Mode. When the COM20051+ is put

into Emulate mode, the internal microcontroller

is put into a high impedance state, thus allowing

an external In-Circuit Emulator (ICE) to program

the internal peripherals such as the ARCNET

core. The advantage of this approach versus

mapping the peripheral registers into the internal

memory (Special Function) area of the 80C32 is

that dedicated software development tools will

not be necessary to debug application software.

Since a majority of 8051 applications use only

a small portion of the Data Memory space, there

is no penalty paid for used address space.

There will also be no penalty in execution time,

since cycle times for external data memory

accesses and internal direct memory moves are

identical. The network and data acquisition

interrupts can be routed to either of the two

The 80C32 microcontroller core is identical to

the 16MHz Intel 80C32 in all respects except for

the absence of Timer 2. Please refer to the Intel

Embedded Microcontrollers and Processors

Databook, Volume 1, for details regarding the

8051 architecture, peripherals, instruction set,

and programming guide. Note that any access

to the internal ARCNET core or any external

memorry access is reflected on the pins of the

COM20051+.

The following differences apply to the

COM20051+:

1. Oscillator frequency is 40MHz instead of

16MHz. This is necessary to derive a

20MHz clock for the ARCNET core. The

processor still operates at 16MHz.

2. nEA/VPP pin - This pin must be tied to

ground for normal internal processor

operation. When tied to VCC, the

COM20051+ will enter the Emulate mode.

3. Power Down operation - the Power Down

mode can only be used in conjunction when

the internal oscillator is being used. If an

external oscillator is used and the Power

Down mode is invoked, damage may result

to the oscillator and to the COM20051+.

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