CP2105-F01-GM View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

CP2105-F01-GM

SINGLE-CHIP USB TO UART BRIDGE

Silicon Laboratories 

CP2105

4. QFN-24 Package Specifications

Figure 3. QFN-24 Package Drawing

Table 8. QFN-24 Package Dimensions

Dimension Min

Typ

Max

Dimension Min

Typ

Max

A

0.70

0.75

0.80

A1

0.00

0.02

0.05

b

0.18

0.25

0.30

D

4.00 BSC.

D2

2.55

2.70

2.80

e

0.50 BSC.

E

4.00 BSC.

E2

2.55

2.70

2.80

L

0.30

0.40

0.50

L1

0.00

—

0.15

aaa

—

—

0.15

bbb

—

—

0.10

ddd

—

—

0.05

eee

—

—

0.08

Z

—

0.24

—

Y

—

0.18

—

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC Solid State Outline MO-220, variation WGGD except for

custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body

Components.

10

Rev. 1.0

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