CP2120 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

CP2120

SPI TO I2C BRIDGE AND GPIO PORT EXPANDER

Silicon Laboratories 

CP2120

Internal Register Definition 10. EDGEINT: Edge Triggered Interrupt Enable

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

EIF

EIE

EIT

Rsvd

Rsvd

Rsvd

Rsvd

Rsvd

Bit 7

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

Bit 0

Internal Register Address:

Reset Value:

Bit 7:

Bit 6:

Bit 5:

Bit 4–Bit 0:

0x08

0x00

EIF: Edge Triggered Interrupt Flag

0: No edge triggered event has occurred on the EI_INT pin.

1: Edge-triggered event has occurred on the EI_INT pin.

EIE: Edge Triggered Interrupt Enable

0: Edge Triggered interrupts disabled.

1: Edge Triggered interrupts enabled.

EIT: Edge Triggered Interrupt Trigger

0: Interrupt triggered on negative-to-positive digital transition on the EI_INT port

pin.

1: Interrupt triggered on positive-to-negative digital transition on the EI_INT port

pin.

Not used.

Rev. 1.0

21

Share Link: