CDB4382 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CDB4382 Datasheet PDF : 42 Pages
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CS4382
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C® FORMAT
(For KQZ TA = -10°C to +70°C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF)
Parameter
Symbol
Min
SCL Clock Frequency
fscl
-
RST Rising Edge to Start
tirs
500
Bus Free Time Between Transmissions
tbuf
4.7
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
Clock Low time
tlow
4.7
Clock High Time
thigh
4.0
Setup Time for Repeated Start Condition
tsust
4.7
SDA Hold Time from SCL Falling
(Note 19)
thdd
0
SDA Setup time to SCL Rising
tsud
250
Rise Time of SCL and SDA
trc, trc
-
Fall Time SCL and SDA
tfc, tfc
-
Setup Time for Stop Condition
tsusp
4.7
Acknowledge Delay from SCL Falling
(Note 20)
tack
-
Max
100
-
-
-
-
-
-
-
-
1
300
-
(Note 21)
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
Notes:
19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
21.
--------1---5----------
256 × Fs
for Single-Speed Mode,
--------1---5----------
128 × Fs
for Double-Speed Mode,
-------1---5--------
64 × Fs
for Quad-Speed Mode.
SDA
001100
ADDR
AD0
R/W ACK
Note 1
DATA
1-8
ACK
DATA
1-8
ACK
SCL
Start
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 3. Control Port Timing - I²C Format
DS514F2
11
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