CDB4383 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CDB4383 Datasheet PDF : 40 Pages
| |||
CS4383
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT (For KQ TA
= -10 to +70 °C; For BQ TA = -40 to +85 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC,
CL = 30 pF)
Parameter
Symbol
Min
SCL Clock Frequency
fscl
-
RST Rising Edge to Start
tirs
500
Bus Free Time Between Transmissions
tbuf
4.7
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
Clock Low time
tlow
4.7
Clock High Time
thigh
4.0
Setup Time for Repeated Start Condition
tsust
4.7
SDA Hold Time from SCL Falling
(Note 17)
thdd
0
SDA Setup time to SCL Rising
tsud
250
Rise Time of SCL and SDA
trc, trc
-
Fall Time SCL and SDA
tfc, tfc
-
Setup Time for Stop Condition
tsusp
4.7
Acknowledge Delay from SCL Falling
(Note 18)
tack
-
Max
100
-
-
-
-
-
-
-
-
1
300
-
(Note 21)
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
Notes: 19.
20.
21.
Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
2---5---6--1---×5-----F---s- for Single-Speed Mode, 1---2---8--1---×5-----F---s- for Double-Speed Mode, 6---4----1-×--5---F---s- for Quad-Speed Mode.
RST
t irs
Stop
S ta rt
SDA
SCL
t buf
t hdst
t h igh
t
low
t
hdd
t sud
t ack
R epe ate d
S ta rt t rd
t hdst
S to p
t fd
t fc
t susp
t sust
t rc
Figure 3. Control Port Timing - I2C Format
10
Share Link: 