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CDB4383 View Datasheet(PDF) - Cirrus Logic

Part Name
Description
Manufacturer
CDB4383 Datasheet PDF : 40 Pages
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CS4383
SWITCHING CHARACTERISTICS (For KQ TA = -10 to +70 °C; For BQ TA = -40 to +85 °C; VLS =
1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30pF)
Parameters
MCLK Frequency
Symbol
Min
Typ
Max
Units
(Note 16)
Single Speed Mode
Double Speed Mode
1.024
-
6.400
-
51.2
MHz
51.2
MHz
Quad Speed Mode
6.400
-
51.2
MHz
MCLK Duty Cycle
40
50
60
%
Input Sample Rate
LRCK Duty Cycle
Single Speed Mode Fs
4
-
50
kHz
Double Speed Mode Fs
50
-
100
kHz
Quad Speed Mode Fs
100
-
200
kHz
45
50
55
%
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
tsclkl
20
-
tsclkh
20
-
tsclkw
--------2---------
-
MCLK
-
ns
-
ns
-
ns
(Note 17) tsclkw
--------4---------
-
MCLK
-
ns
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
tslrd
20
-
tslrs
20
-
tsdlrs
20
-
tsdh
20
-
-
ns
-
ns
-
ns
-
ns
Notes: 16. See Table 5 on page 26 for suggested MCLK frequencies
17. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.
.
LRCK
t slrd
t slrs
t sclkh
t sclkl
SCLK
t sd lrs
t sd h
SDATA
Figure 1. Serial Mode Input Timing
8

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